1.Field of the Invention
This invention relates generally to a signed magnitude floating point addition and subtraction system and, more particularly, to a versatile floating point adder which performs high speed floating point addition and subtraction in a signed magnitude format.
2. Description of the Prior Art
The signed magnitude data format consists of an exponent field, a mantissa field, and a sign bit field used to represent floating point binary numbers. A floating point binary number N can be represented as: EQU N=(-1).sup.S .times.2.sup.E-b .times.(1.F)
where S is the sign field, E is the exponent field, F is the fraction or mantissa field, and b is a bias.
In floating point addition and/or subtraction operations, the following basic eight steps are performed sequentially to actually execute the addition or subtraction operation.
(1) The two exponent fields of the floating point numbers are compared to determine an exponent difference.
(2) The fractional part (mantissa) of the floating point number having the smaller exponent is "denormalized" i.e., the specified mantissa is shifted so as to produce floating point numbers having the same exponent.
(3) The denormalized mantissa is added to or subtracted from the mantissa with the larger exponent or vice versa, depending upon the signs of the operands.
(4) The sign of the result is determined.
(5) The result is converted into a signed magnitude representation.
(6) The number of leading zeros of the result is determined. It is important to realize that leading zeros can result from addition and/or subtraction operations in which the high order bits cancel one another.
(7) The result is normalized, and correspondingly the resulting exponent is adjusted in concert with the normalization performed for the fractional part of the result.
(8) The mantissa is rounded, and the exponent is incremented by 1 if a rounding overflow occurs.
In high speed computation oriented systems, the speed of multiplying floating point binary numbers approaches the speed of addition. In previous pipelined multiply/accumulate architectures, the time required for adding or subtracting floating point binary numbers has been significantly less than the time required for multiplication.
In the conventional design known as the floating point "multiply/accumulate design", the architecture is designed to handle mantissa addition in a two's complement format. This architecture requires conversion of the input mantissa from a signed magnitude format into a two's complement format so that subtraction can be performed. Special hardware is required to perform this conversion function. In this same design it is necessary to convert the final floating point mantissa result from the two's complement format into signed magnitude format. In this case the mantissa data is simply inverted to perform the conversion, which reduces accuracy in the final mantissa result. The final result does not require any additional two's complement hardware to perform this conversion and preserves computation speed, at the cost of losing one bit of accuracy in the final result. Accordingly, either less speed, additional hardware, or reduced accuracy of result is a penalty encountered when floating-point subtraction is to be performed using two's complement format internal to the architecture and signed magnitude format external to the architecture.
As indicated in the previous paragraph, the conventional "multiply/accumulate" chip converts the single precision input signed magnitude format into a two's complement format in order to perform both addition and subtraction operations. This does not satisfy the need for double precision computations in a floating point architecture in which the addition/subtraction computations are performed at the same speed as multiplication computations and all operations are performed on double precision data. Thus, a more versatile design is required to meet this need.